CY62256VNLL-70ZXI资料

CY62256VN

256K (32K x 8) Static RAM

Features

•Temperature Ranges—Commercial: 0°C to 70°C—Industrial: –40°C to 85°C—Automotive-A: –40°C to 85°C—Automotive-E: –40°C to 125°C•Speed: 70 ns

•Low voltage range: 2.7V–3.6V•Low active power and standby power

•Easy memory expansion with CE and OE features•TTL-compatible inputs and outputs•Automatic power-down when deselected•CMOS for optimum speed/power

•Available in standard Pb-free and non Pb-free 28-lead (300-mil) narrow SOIC, 28-lead TSOP-I and 28-lead Reverse TSOP-I packages

Functional Description[1]

The CY62256VN family is composed of two high-performanceCMOS static RAM’s organized as 32K words by 8 bits. Easymemory expansion is provided by an active LOW chip enable(CE) and active LOW output enable (OE) and tri-state drivers.These devices have an automatic power-down feature,reducing the power consumption by over 99% whendeselected.

An active LOW write enable signal (WE) controls thewriting/reading operation of the memory. When CE and WEinputs are both LOW, data on the eight data input/output pins(I/O0 through I/O7) is written into the memory locationaddressed by the address present on the address pins (A0through A14). Reading the device is accomplished by selectingthe device and enabling the outputs, CE and OE active LOW,while WE remains inactive or HIGH. Under these conditions,the contents of the location addressed by the information onaddress pins are present on the eight data input/output pins.The input/output pins remain in a high-impedance state unlessthe chip is selected, outputs are enabled, and write enable(WE) is HIGH.

Logic Block Diagram

INPUTBUFFER

A10A9A8A7A6A5A4A3A2CEWEOE

A14A13A12A11A1A0ROW DECODERI/O0I/O1

SENSE AMPSI/O2I/O3I/O4I/O5

32K x 8

YARRA

COLUMNDECODER

POWERDOWN

I/O6I/O7

Note:

1.For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

CypressSemiconductorCorporationDocument #: 001-06512 Rev. *A

•198 Champion Court•

SanJose,CA 95134-1709•408-943-2600

Revised August 3, 2006

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Product Portfolio

CY62256VN

Power Dissipation

VCC Range (V)

ProductCY62256VNLLCY62256VNLLCY62256VNLLCY62256VNLL

Range Ind’lAutomotive-AAutomotive-E

Min.2.72.72.7

Typ.[2]3.03.03.03.0

Max.3.63.63.63.6

Com’l 2.7Operating, ICC (mA)Typ.[2]11

Max.30

11 3011 3011 30Standby, ISB2 (µA)Typ.[2]0.1

Max.10

0.1 5 0.1 100.1 130

Pin Configurations

Narrow SOICTop View

A5

A6A7A8A9A10A11A12A13A14I/O0I/O1I/O2GND

12345671011121314

2827262524232221201918171615

VCCWEA4A3A2A1OEA0CEI/O7I/O6I/O5I/O4I/O3

OEA1A2A3A4WEVCCA5A6A7A8A9A10A11

222324252627281234567

21201918171615141312111098

TSOP ITop View(not to scale)

A0CEI/O7I/O6I/O5I/O4I/O3GNDI/O2I/O1I/O0A14A13A12

A11A10A9A8A7A6A5VCCWEA4A3A2A1OE

765432128272625242322

101112131415161718192021

TSOP IReverse Pinout

Top View(not to scale)

A12A13A14I/O0I/O1I/O2GNDI/O3I/O4I/O5I/O6I/O7CEA0

Pin Definitions

Pin Number11–13, 15–192720221428

Type

A0–A14. Address Inputs

I/O0–I/O7. Data lines. Used as input or output lines depending on operation

WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conductedCE. When LOW, selects the chip. When HIGH, deselects the chip

OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave asoutputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pinsGND. Ground for the device

Input/OutputInput/ControlInput/ControlInput/ControlGround

Description

1–10, 21, 23–26Input

Power SupplyVCC. Power supply for the device

Note:

2.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25°C, and tAA = 70 ns.

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Maximum Ratings

(Above which the useful life may be impaired. For user guide-lines, not tested.)

Storage Temperature ................................–65°C to + 150°CAmbient Temperature with

Power Applied............................................–55°C to + 125°CSupply Voltage to Ground Potential

(Pin 28 to Pin 14)..........................................–0.5V to + 4.6VDC Voltage Applied to Outputs

in High-Z State[3]....................................–0.5V to VCC + 0.5VDC Input Voltage.................................–0.5V to VCC + 0.5VOutput Current into Outputs (LOW).............................20 mA

[3]

CY62256VN

Static Discharge Voltage.......................................... > 2001V(per MIL-STD-883, Method 3015)

Latch-up Current.................................................... > 200 mA

Operating Range

Device

RangeIndustrial

Ambient Temperature

(TA)[4]−40°C to +85°C

VCC

CY62256VNCommercial0°C to +70°C 2.7V to 3.6V

Automotive-A−40°C to +85°C Automotive-E−40°C to +125°C

Electrical Characteristics Over the Operating Range

-70

ParameterVOHVOLVIHVILIIXIOZICCISB1

DescriptionOutput HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput Leakage VoltageInput Leakage Current

GND < VIN < VCC

Com’l/Ind’l/Auto-AAuto-E

Output Leakage CurrentGND < VIN < VCC, Output

DisabledVCC Operating Supply VCC = 3.6V, IOUT = 0 mA,Currentf = fMAX = 1/tRCAutomatic CE

Power down Current - TTL Inputs

Automatic CE

Power-down Current- CMOS Inputs

Com’l/Ind’l/Auto-AAuto-EAll Ranges

IOH = −1.0 mAIOL = 2.1 mA

Test Conditions

VCC = 2.7VVCC = 2.7V

2.2–0.5–1–10–1–10

11100

Min.2.4

0.4VCC + 0.3V

0.8+1+10+1+1030300

Typ.[2]Max.

UnitVVVVµAµAµAµAmAµA

VCC = 3.6V, CE > VIH, All RangesVIN > VIH or VIN < VIL, f = fMAX

VCC = 3.6V, CE > VCC – 0.3VCom’lVIN > VCC – 0.3V or VIN < Ind’l/Auto-A

0.3V, f = 0

Auto-E

ISB2

0.1510130

µA

Notes:

3.VIL (min.) = –2.0V for pulse durations of less than 20 ns.4.TA is the “Instant-On” case temperature

Document #: 001-06512 Rev. *APage 3 of 12

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Capacitance[5]

Parameter

CINCOUT

Description

Input CapacitanceOutput Capacitance

Test Conditions

TA = 25°C, f = 1 MHz,VCC = 3.0V

Max.68

CY62256VN

UnitpFpF

Thermal Resistance[5]

Parameter

ΘJAΘJC

DescriptionThermal Resistance (Junction to Ambient)Thermal Resistance (Junction to Case)

Test Conditions

Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board

SOIC68.4526.94

TSOPI87.6223.73

RTSOPI87.6223.73

Unit°C/W°C/W

AC Test Loads and Waveforms

R1

VCCOUTPUT

50 pFINCLUDINGJIG ANDSCOPE

R2

VCCGND

10%

ALL INPUT PULSES90%

90%10%

<5ns

<5ns

Equivalentto:

THÉ VENINEQUIVALENT

Rth

OUTPUT

Vth

Parameter

R1R2RTHVTH

Value1100150051.750

UnitsOhmsOhmsOhmsVolts

Data Retention Characteristics (Over the Operating Range)

ParameterVDRICCDR

Description

VCC for Data RetentionData Retention Current

VCC = 1.4V,

CE > VCC – 0.3V,VIN > VCC – 0.3V or VIN < 0.3VCom’lInd’l/Auto-AAuto-E

0tRC

Conditions[6]Min.1.4

0.1

3650

nsns

Typ.[2]Max.

UnitVµA

tCDR[6]tR[5]Chip Deselect to Data Retention Time

Operation Recovery Time

Data Retention Waveform

DATA RETENTION MODE

VCCCE

Note:

5.Tested initially and after any design or process changes that may affect these parameters.6.No input may exceed VCC + 0.3V.

1.8VtCDR

VDR>1.4V

1.8VtR

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Switching Characteristics Over the Operating Range[7]

CY62256VN

CY62256VN-70

Parameter

Read CycletRCtAAtOHAtACEtDOEtLZOEtHZOEtLZCEtHZCEtPUtPD

Write Cycle[10, 11] tWCtSCEtAWtHAtSAtPWEtSDtHDtHZWEtLZWE

Write Cycle TimeRead Cycle Time

DescriptionMin.70

Max.Unitns

Address to Data Valid

Data Hold from Address ChangeCE LOW to Data ValidOE LOW to Data ValidOE LOW to Low-Z[8]OE HIGH to High-Z[8, 9]CE LOW to Low-Z[8]CE HIGH to High-Z[8, 9]CE LOW to Power-upCE HIGH to Power-down

7060600050300010510

707035252570

nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

CE LOW to Write EndAddress Set-up to Write EndAddress Hold from Write EndAddress Set-up to Write StartWE Pulse WidthData Set-up to Write EndData Hold from Write EndWE LOW to High-Z[8, 9]WE HIGH to Low-Z[8]25

10

nsns

Notes:

7.Test conditions assume signal transition time of 5 ns or less timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOL/IOH and 100-pF load capacitance.

8.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.9.tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

10.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can

terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.11.The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

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Switching Waveforms

Read Cycle No. 1[12, 13]

tRC

ADDRESS

tOHA

DATA OUT

PREVIOUS DATA VALID

tAA

CY62256VN

DATA VALID

Read Cycle No. 2[13, 14]

CE

tACE

OE

tDOE

DATA OUT

tLZOE

HIGH IMPEDANCE

tLZCE

VCCSUPPLYCURRENT

tPU

50%

DATA VALID

tPD

ICC

50%

ISB

tHZOEtHZCE

tRC

HIGH IMPEDANCE

Write Cycle No. 1 (WE Controlled)[10, 15, 16]

tWC

ADDRESS

CE

tAW

WE

tSA

tPWE

tHA

OE

tSD

DATA I/O

NOTE 17tHZOE

Notes:

12.Device is continuously selected. OE, CE = VIL.13.WE is HIGH for read cycle.

14.Address valid prior to or coincident with CE transition LOW.15.Data I/O is high impedance if OE = VIH.

16.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.17.During this period, the I/Os are in output state and input signals should not be applied.

tHD

DATAINVALID

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Switching Waveforms (continued)

Write Cycle No. 2 (CE Controlled)[10, 15, 16]

tWC

ADDRESS

CE

tSA

tAW

WE

tSD

DATA I/O

DATAINVALID

tHD

tHA

tSCE

CY62256VN

Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]

tWC

ADDRESS

CE

tAW

tSA

WE

tSD

DATA I/O

NOTE 17tHZWE

DATAINVALID

tLZWE

tHDtHA

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CY62256VN

Typical DC and AC Characteristics

NORMALIZED SUPPLY CURRENTNORMALIZED SUPPLY CURRENTSTANDBY CURRENT

vs. SUPPLY VOLTAGE1.81.61.4

CCI 1.2DEZ1.0ILA0.8MRO0.6TA= 25°C

N0.40.26804..8..261122.2..33SUPPLY VOLTAGE (V)

NORMALIZED ACCESS TIMEvs. SUPPLY VOLTAGE

2.5A2.0At DEZI1.5LAMTRA = 25°C

O1.0N0.5

0.01.65

2.12.63.13.6

SUPPLY VOLTAGE (V)

Document #: 001-06512 Rev. *Avs. AMBIENT TEMPERATURE

vs. AMBIENT TEMPERATURE1.4V3.0CC = 3.0V

1.22.5CC1.0

2.0

0.8Aµ1.5 V23.0.6BS =I1.03 cVc0.40.5ISB

0.20.0

0.0−55

25

125

–0.5−55

25

105

AMBIENT TEMPERATURE (°C)AMBIENT TEMPERATURE (°C)

NORMALIZED ACCESS TIMEOUTPUT SINK CURRENTvs. AMBIENT TEMPERATURE)14vs. OUTPUT VOLTAGE1.6

AmV(CC = 3.0V 12TA1.4NAER10R1.2UC8 K1.0NIS6 TU40.8PTTA = 25°C

UO20.6−055

25125

0.0

1.0

2.03.0

AMBIENT TEMPERATURE (°C)OUTPUT VOLTAGE (V)

OUTPUT SOURCE CURRENT)vs. OUTPUT VOLTAGEAm–14( TNE–12RRUC–10 ECR–8UOS–6

TTUA = 25°C

P–4TUO00.0

0.5

1.0

1.52

2.5

OUTPUT VOLTAGE (V)

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Typical DC and AC Characteristics (continued)

TYPICAL ACCESS TIME CHANGEvs. OUTPUT LOADING30.0

NORMALIZED ICCDELTA t A (ns)A25.0T= 25°CA

VCC = 3V20.015.010.05.00.0

0

200

400

600

8001000

0.50

1

1020CY62256VN

NORMALIZED ICC vs. CYCLE TIME1.25

VCC = 3.0V1.00

TA = 25°CVIN = 0.5V

0.75

30CAPACITANCE (pF)

CYCLE FREQUENCY (MHz)

Truth Table

CEHLLL

WEXHLH

OEXLXH

Inputs/OutputsHigh-ZData OutData InHigh-Z

ReadWrite

Mode

Deselect/Power-down

Active (ICC)Active (ICC)Active (ICC)

Power

Standby (ISB)

Deselect, Output Disabled

Ordering Information

Speed(ns)70

Ordering CodeCY62256VNLL-70SNCCY62256VNLL-70SNXCCY62256VNLL-70ZCCY62256VNLL-70ZXCCY62256VNLL-70SNXICY62256VNLL-70ZICY62256VNLL-70ZXICY62256VNLL-70ZRICY62256VNLL-70ZRXICY62256VNLL-70ZXACY62256VNLL-70SNXECY62256VNLL-70ZXECY62256VNLL-70ZRXE

51-8507151-8509251-8507151-8507451-8507451-8507151-85071PackageDiagram

Package Type

28-lead (300-mil) Narrow SOIC (Pb-Free)28-lead TSOP I

28-lead TSOP I (Pb-Free)

51-8509228-lead (300-mil) Narrow SOIC (Pb-Free)

28-lead TSOP I

28-lead TSOP I (Pb-Free)28-lead Reverse TSOP I

28-lead Reverse TSOP I (Pb-Free)28-lead TSOP I (Pb-Free)

28-lead (300-mil) Narrow SOIC (Pb-Free)28-lead TSOP I (Pb-Free)28-lead Reverse TSOP I (Pb-Free)

Automotive-AAutomotive-EIndustrialOperatingRangeCommercial

51-8509228-lead (300-mil) Narrow SOIC

Please contact your local Cypress sales representative for availability of other parts

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CY62256VN

Package Diagrams

28-lead (300-mil) SNC (Narrow Body) (51-85092)

51-85092-*B

28-lead TSOP 1 (8 × 13.4 mm) (51-85071)

51-85071-*G

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Package Diagrams (continued)

28-lead Reverse TSOP 1 (8 × 13.4 mm) (51-85074)

CY62256VN

51-85074-*F

All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 001-06512 Rev. *APage 11 of 12

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to beused for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize itsproducts for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypressproducts in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Document History Page

Document Title: CY62256VN 256K (32K x 8) Static RAMDocument Number: 001-06512REV.***A

ECN NO.Issue Date4265044854

See ECNSee ECN

Orig. of ChangeNXRNXR

New Data Sheet

Added Automotive product

Updated ordering Information table

Description of Change

CY62256VN

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