专利内容由知识产权出版社提供
专利名称：METHOD AND APPARATUS FOR
SUPPRESSING A DETERMINISTIC CLOCKJITTER
发明人：Chia-Liang Lin申请号：US14014445申请日：20130830
公开号：US20150061787A1公开日：20150305
专利附图：
摘要：A method for generating an output clock comprising: detecting a timingdifference between a first input clock and a second input clock to generate a phase error
signal; generating a masked phase error signal by masking the phase error signal basedon a deterministic jitter indicator signal; generating an oscillator control signal by filteringthe masked phase error signal; and generating the output clock in accordance with theoscillator control signal.
申请人：Realtek Semiconductor Corp.
地址：Hsinchu TW
国籍：TW
更多信息请下载全文后查看
