专利内容由知识产权出版社提供
专利名称：Method for improving planarization of an
ILD layer
发明人：Chiu-Te Lee申请号：US09620236申请日：20000720公开号：US06333221B1公开日：20011225
专利附图：
摘要：An improved embedded DRAM fabricating process is disclosed. The methodincludes first forming a first dielectric layer on the surface of a semiconductor wafercovering a memory region and a logic region that are previously defined on the
semiconductor wafer, forming a conductive layer over the first dielectric layer, forming atleast one dummy pattern over the logic region and a plurality of storage nodes over thememory region in the conductive layer, forming an insulating layer and a top electrodeon each of the storage nodes, and forming a second dielectric layer on the surface of thesemiconductor wafer that covers the top electrode and the dummy pattern. The seconddielectric layer fills the spaces between the dummy pattern.
申请人：UNITED MICROELECTRONICS CORP.
代理人：Winston Hsu
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