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专利名称：Analog multiplier using quadritail circuits发明人：KATSUJI KIMURA申请号：AU5312394申请日：19940111公开号：AU668785B2公开日：19960516
摘要：A multiplier containing first and second quadritail cells. The first quadritail cellhas a first pair of first and second transistors, a second pair of third and fourth
transistors, and a first constant current source for driving the first and second pairs. Thesecond quadritail cell has a third pair of fifth and sixth transistors, a fourth pair of seventhand eighth transistors, and a second constant current source for driving the third andfourth pairs. Each of the first to fourth pairs has output ends coupled together. A firstinput voltage is applied between input ends of the first and fourth transistors and isapplied between input ends of the fifth and eighth transistors. A second input voltage isapplied between input ends coupled together of the second and third transistors andthe input ends coupled together of the sixth and seventh transistors. The output ends ofthe first and fourth pairs are coupled together to form one of differential output ends,and those of the second and third pairs are coupled together to form the other of thedifferential output ends thereof. At least one of the first and second input voltages canbe expanded in linear range at a low power source voltage such as 3 or 3.3 V.
申请人：NEC CORPORATION
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