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专利名称：Analog multiplier using quadritail circuits发明人：Katsuji Kimura申请号：US08/120462申请日：19930914公开号：US054448A公开日：19950822
摘要：A multiplier having first and second quadritail circuits, each of which has twopairs of transistors whose capacities are the same, respectively, and is driven by aconstant current source. In the first quadritail circuit, input ends of a first pair arerespectively applied with voltages .+-.(V.sub.1 +V.sub.2), and input ends of a second pairare connected in common to be biased by a middle point voltage of the voltage appliedbetween the input ends of the first pair. In the second quadritail circuit, input ends of athird pair are respectively applied with voltages .+-.(V.sub.1 -V.sub.2), and input ends of afourth pair are connected in common to be biased by a middle point voltage of thevoltage applied between the input ends of the third pair. Common-connected outputends of the first and fourth pairs are respectively connected in common to form one ofdifferential output ends, and common-connected output ends of the second and thirdpairs are connected in common to form the other of the differential output ends.Simplification of circuit configuration and reduction of current consumption areaccomplished.
申请人：NEC CORPORATION
代理机构：Sughrue, Mion, Zinn, Macpeak & Seas
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