全加器的VHDL程序
全加器： LIBRARY
IEEE; USE
IEEE.STD_LOGIC_11.ALL; ENTITY
full_adder IS
PORT (Ain,Bin ,Cin :IN STD_LOGIC;
Sum,Co: out STD_LOGIC ); end full_adder; ARCHITECTURE rtl OF
full_adder
IS
BEGIN
Sum<=Ain Xor Bin
xor Cin ;
Co<= (Ain and
Bin) or ( Ain Xor Bin ) and Cin ; END rtl;
